(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the creation of flash memory cells.
(2) Description of the Prior Art
Read Only Memory (ROM) devices, also referred to as mask-programmed devices, are non-volatile memories into which data is permanently stored through the use of custom masks during the fabrication of the devices. A desired bit pattern of the memory is in this manner imbedded into the device, each bit pattern being aimed at one particular application of the device. Only read operations can be performed, changes of the data contained in the memory cannot be made after the device has been fabricated. Customization of the device is however economically feasible since only one mask has to be used for the fabrication of the device. ROM devices have been implemented using bipolar, NMOS and CMOS technologies. A typical application of ROM devices is in the interface between central processors and other devices that make up a data processing system whereby the ROM devices eliminate wait states and improve system speed.
The different data elements are stored in a ROM device by the presence or absence of a data path that is formed between a word line (the access path) to a bit line (the sense line). No data element will be provided if the word line and the bit line are not joined by a circuit element. If therefore the word line of a ROM is activated, the presence of a signal on the bit line indicates that a "1" is stored in that data element (bit location). The absence of a signal on the bit line indicates that a "0" is stored in that bit location. The implementation of the ROM device uses either a complement of NOR functions or a complement of NAND functions. The imbedding of data in ROM devices (zero or one bit conditions) takes place by selectively omitting a contact.
Field-programmable ROM (PROM) devices are ROM devices that are typically manufactured in small quantities, these devices are programmed individually in order to save overall manufacturing costs. Some ROM devices are manufactured such that data, once entered into the device, cannot be erased while other ROM devices allow the data to be erased and re-entered after the device has been manufactured. Initially, such devices predominantly used bipolar technology but these devices are at this time also implemented using MOS technology. The erasable PROM's (EPROM's) depend on the long-term retention of data, this data is retained as an electronic charge and is stored on a polysilicon gate of a MOS device. The term floating in this structure refers to the fact that no electrical connections exist to the gate that retains the electrical charge. The charge is therefore transferred from the silicon substrate through an insulator. In order for the charge to be erased, the stored charge must be erased from the floating gate. This erasure can be achieved by exposing the EPROM to UV light for a time of up to about 20 minutes. This UV light creates a discharge path for the floating gate. EPROM cells typically consist of only one transistor making it possible to create very high-density arrays of EPROM cells. The UV light that is required to erase EPROM cells however brings with it the requirement that EPROM cells must be packaged in relatively expensive ceramic packages that contain a UV-transparent window. They must also, during the process of erasure, be removed from the printed circuit board and placed in a special UV eraser. To negate these disadvantages, electrically erasable PROM's (EEPROM's) have been created. These EEPROM devices are implemented using either floating-gate tunnel oxide (FLOTOX) MOS devices or using textured-polysilicon floating-gate MOS devices. FLOTOX MOS devices consist of a MOS transistor with two poly gates, the textured-polysilicon floating-gate MOS devices consists of three layers of poly that partially overlap to create a cell that acts as three MOS devices that are connected in series. In this arrangement, the floating-gate MOS device is formed in the middle of the poly structure, this device is encapsulated in SiO.sub.2 in order to provide this device with high charge retention. The tunneling that is required to affect the charge transfer will, in this case, take place from one poly structure to another rather than from the substrate to the floating gate. Textured poly gates are programmed by causing electrons to flow (tunnel) from the floating poly structure to poly 3. A relatively high voltage is established on the poly 3 during both the programming and the erase operations. The drain voltage determines whether the tunneling occurs from poly 1 to the floating gate or from the floating gate to poly 3. The drain voltage therefore determines the final state of the memory cell.
Yet another design of the EEPROM cells is the flash EEPROM which has been named as such because all the memory cells can be rapidly and electrically erased in one operation. This operation of memory erasure can be performed on the entire memory array or on selected parts of the memory array down to the erasure of individual bytes within the memory array. The erasing mechanism of the flash EEPROM consists of tunneling off the region between the floating gate and the drain region of the MOS device. Programming the flash EEPROM is carried out by hot carrier injection into the gate of the MOS device. Flash EEPROM typically will use the erasure of relatively large regions of memory, the floating gate EEPROM's typically incorporate a separate select transistor which allows for the erasure of individual bytes.
Most flash EEPROM's use a double poly structure whereby the upper poly forms the control gate and the word lines of the structure while the lower poly is the floating gate. In a typical structure, the control-gate poly overlaps the channel region that is adjacent to the channel under the floating gate. The extension of the control gate over the channel region is referred to as the series enhancement-mode transistor and is required because when the cell is erased, a positive charge remains on the floating gate inverting the channel under floating gate. The series enhancement-mode transistor prevents the flow of current from the source to the drain regions of the MOS device.
A memory array is addressed via address decoding circuitry that consists of a word line or X-line decoder and a bit line or Y-line decoder. The memory cells that are at the intersection of the X-line and Y-line decoders form the memory cells that are addressed by the address that has been provided to the decoders.
FIGS. 1a and 1b show the conventional structure of an EPROM cell array. Where FIG. 1a shows a cross section of an array of EPROM cells that is taken in the X-direction, FIG. 1b shows a cross section of this array in the Y-direction and taken along the line 1b-1b' of FIG. 1a. The active regions in the surface of the substrate 10 are electrically isolated by the field oxide layers 12. For the purpose of the example that is shown in FIGS. 1a and 1b, the substrate selected is a p-type conductivity substrate. As a first step in the creation of the EPROM device, a layer (not shown) of sacrificial silicon oxide is grown on the surface of the p-type substrate to clean the edge of the field oxide regions 12, that is to remove or limit the extend of the "bird's beak" (regions of field oxide that laterally extend from the body of the field oxide region) that is typically part of the field oxide regions. The layer of sacrificial silicon oxide is then stripped before growth of the tunnel oxide (layer 14) in the active regions of the surface of the substrate. The thin layer 14 of tunnel oxide is formed over the exposed surface of the substrate 10 including the surface of the field oxide layers 12. A layer of polysilicon (poly 1, not shown) is deposited over the surface of the layer 14 of gate oxide, this layer of poly is selectively etched and forms the layers 15 that function as the floating gates 15 of the EPROM devices. A second layer 16 of inter-polysilicon ONO is deposited over the surface of the floating gates 15. The gate structure of the EPROM devices is completed by the overlying layer 18 of poly 2 which forms the control gate strip 18 that runs in the X-direction of the memory array interconnecting a plurality of control gates in that direction. The self-aligned floating gates are formed at the same time by selective etching. While masking one side of the gate electrode stack, an n-type implant is performed on the other side of the gate electrode stack and into the surface of the substrate 10 forming the n-type source (28) regions on the unmasked side of the gate electrode stack and in the surface of the substrate 10. The n-type implanted ions can be further driven into the surface of the substrate to make the source regions 28 deep regions. Ion implants of n-type are performed into the substrate to form (more shallow) N+ doped drain regions 26 on the other side of the gate electrode stack from the source regions 28. An insulating layer 20 is deposited over the structure that also covers the gate control strips 18. Openings are made in this layer of insulation above the drain regions 26. Electrical contact is established with the drain regions 26 of the structure by means of a plurality of metal strips 22 that are created in the Y-direction. On the other hand, the source region 28 is contacted (not shown in FIG. 1b) by metal lines that have been extended in the X-region of the array. A coating 24 of insulation overlies that metal strips 22.
For the EPROM cells that have been created in accordance with FIGS. 1a and 1b, when the drain region 26 and the control strips 18 are kept at a high voltage while the source region 28 is kept at a low or ground voltage, hot electrons that are created in the channel region between the source and drain regions are injected into the floating gate. A "0" value is therefore stored in the memory cell. When the voltage that is applied is reversed, the electrons that have accumulated in the memory cell are discharged resulting in a "1" being stored in the memory cell.
U.S. Pat. Nos. 5,721,441 (Lee) and 5,658,814 (Lee) show a method and structure for a Flash memory Cell comprising: double floating poly and double poly etch process to form overlapping TXs, see FIGS. 3 through 7, also see claim 1. This is close to the invention.
U.S. Pat. No. 5,107,313 (Kohda et al.) shows a flash memory process with closely spaced FG's and one overlying CG. This is close to the present invention, see FIG. 10.
U.S. Pat. Nos. 5,744,834 (Lee), 5,620,913 (Lee) and 5,610,419 (Tanaka) shows other memory process.